1. Field of the Invention
The present invention relates generally to phase-locked loops (PLLs).
2. Description of Related Art
Phase-locked loops are widely used in electronic devices, such as computers, telecommunications equipment and radio. However, known PLLs have been insufficiently noise insensitive.
FIG. 1 illustrates a known PLL 100, which is used to maintain an output frequency ωout to be a multiple times of a reference frequency ωref. The PLL 100 has a phase and frequency detector (PFD) 101, a charge pump 102, a loop filter 103, a voltage-controlled oscillator (VCO) 104 and a divider 105. The VCO 104 has a voltage supply 1041 which as shown may be, e.g., a high power supply rejection (PSR) regulator, a voltage to current converter 1042 and a current-controlled oscillator (ICO) 1043. The ICO 1043 may be, e.g., a ring based oscillator. The voltage to current converter 1042, having a voltage to current converting rate gm=IC/Vctrl, may generate a control current IC in proportion with a control voltage Vctrl from the loop filter 103. The ICO 1043, having a frequency tuning gain KICO=ωout/Ic, may output a frequency ωout based on the control current IC. The divider 105 is on the feedback route from the output of the ICO 1043 to the input of the PFD 101, and may divide the output frequency ωout by an integer N and send a feedback frequency, ωfb=ωout/N, to the input of the PFD 101.
The PFD 101 may compare the feedback frequency ωfb with the reference frequency ωref. When ωfb is lower than the reference frequency ωref, the PFD 101 may output switching signals PU and PD to the charge pump 102, closing a switch 1021 and keeping a switch 1022 open, so as to charge a charge storage device C1 in the loop filter 103. Consequently, the control voltage Vctrl at the output of the loop filter 103 is up, the control current IC supplied to the ICO 1043 is up, and the output frequency ωout is up until it equals N ωref.
When ω is higher than the reference frequency ωref, the PFD 101 may generate switching signals PU and PD to open the switch 1021 and close the switch 1022, so that the charge storage device C1 in the loop filter 103 may discharge via the switch 1022. Consequently, the control voltage Vctrl at the output of the loop filter 103 is down, the control current IC is down, and the output frequency ωout is down, until ωout=N ωref.
When ωfb equals ωref, the PFD 101 may keep both switches 1021 and 1022 closed to maintain the relationship.
The pole position and zero position of the PLL 100 are:
                              ω          z                =                  1                                    R              1                        ⁢                          C              1                                                          (        1        )                                          ω          p                =                                            1                                                R                  1                                ⁢                                  C                  2                                                      ⁢                          (                              1                +                                                      C                    2                                                        C                    1                                                              )                                ≈                      1                                          R                1                            ⁢                              C                2                                                                        (        2        )            
So the ratio between the pole and zero position is:
                                          ω            p                                ω            z                          =                                            C              1                        +                          C              2                                            C            2                                              (        3        )            
The gain bandwidth of the PLL 100 is:
                              ω          c                ≈                                            I              cp                                      2              *              π                                *                      R            1                    *                      g            m                    *                      K            ICO                    *                      1            N                                              (        4        )            
For the PLL 100, the output phase noise at the output frequency ωout contributed by R1 is:
                              ϕ          n          2                =                  4          *          K          *          T          *                      R            1                    *                                    (                                                g                  m                                *                                                      K                    ICO                                    s                                            )                        2                                              (        5        )            
wherein K is the Boltzmann constant, T is a temperature value, and s=jω, which is a variable in frequency domain.
One limitation of the known PLL 100 is its high frequency tuning gain (KVCO), which is the frequency/voltage gain of the VCO. The high frequency tuning gain, together with a wide loop bandwidth used to suppress phase noise, may make the PLL more sensitive to the noise from the PFD, the charge pump and the loop filter. Therefore, it may be desirable to provide a PLL which may have a decreased frequency tuning gain KVCO and the wide loop bandwidth.
Another limitation of the known PLL 100 is that the loop filter 103 may occupy a large chip area when being integrated on a chip. One known solution uses an active loop filter, but the active device may bring additional noise. Another known solution uses a passive feed forward loop filter with noiseless resistor multiplication, but it may increase sensitivity to switching glitches of the charge pump. Therefore, it may be desirable to provide a PLL with a loop filter which has high chip area efficiency but low noise and switching glitch sensitivity.